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dual 256-position i 2 c compatible digital potentiometer ad5243/ad5248 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 2-channel, 25 6 - position end-to-end r e s istance: 2.5 k? , 10 k?, 50 k?, and 10 0 k? compact msop-10 ( 3 mm 4. 9 mm) package fast settling ti me: t s = 5 s typ on power-up full re ad/write of wiper register power-on preset to midscale extra package address decod e pins ad 0 and ad1 (a d5248 only ) computer software replaces c in factory pr ogramming applications single supply: 2.7 v to 5.5 v low temperature coefficient: 35 ppm/c low power: i dd = 6 a max wide operatin g temperature: ?40 c to + 125 c evaluation board available applic ati o ns systems calibr ations electronics level settings mechanical trimmers? replacement in new d e signs permanent fac t ory pcb settin g transducer adj u stment of pre ssure, tempera t ure, position, chemical, and optical sensors rf amplifier bi asing automotive e l ectronics adjustment gain control and offset a d just ment func tio n a l block di agrams a1 v dd g nd sda scl w1 wiper register 1 pc interface ad5243 04109-0-001 b1 a2 w2 wiper register 2 b2 f i g u re 1. a d 52 43 v dd g nd sda scl ad0 ad1 w1 rdac register 1 address decode serial input register ad5248 b1 w2 rdac register 2 b2 / 8 04109-0-002 f i g u re 2. a d 52 48 general description the ad5243 and ad5248 p r o v ide a com p ac t 3 mm 4.9 mm p a c k a g e d s o l u tio n f o r d u al 256-p o si tio n ad j u s t m e n t a p p l ic a - ti o n s. th e s e de vi ce s pe rf o r m th e sa m e e l ectr o n ic a d j u s t m e n t f u n c tion as a 3 - t e r m inal m e c h anical p o t e n t iomet e r (ad5243) o r a 2-t e r m inal va r i a b le r e sis t o r (ad5248). a v ai la b l e in f o ur dif f er en t e n d - t o -end r e sist an c e va l u es (2.5 k?, 10 k?, 50 k?, a nd 100 k?), thes e lo w t e m p era t ur e co ef f i cien t de vices a r e idea l for h i g h a c c u r a c y and s t abi l it y v a r i abl e re s i st a n c e a d j u st me n t s . the wi p e r s e t t i n gs a r e co n t r o l l a b l e t h r o ug h t h e i 2 c co m p a t ib l e dig i t a l in t e r f ace . the ad5248 has extra p a c k a g e addr es s deco de p i n s ad0 and ad1, al lo win g m u l t i p le p a r t s t o sha r e th e s a m e i 2 c 2-wir e b u s on a pc b . th e r e si s t a n ce be tw een th e w i p e r a n d ei t h er end p oin t o f t h e f i xe d r e sis t o r va r i es lin e arl y wi t h r e sp e c t to t h e dig i t a l co de t r a n sfer r e d i n to t h e r d a c l a tch. 1 o p era t ing f r o m a 2.7 v t o 5.5 v p o w e r s u p p l y a nd co n s u m in g l e ss t h an 6 a a l l o w s for u s age i n p o r t abl e b a t t e r y - op e r a t e d ap p l i c at i o n s . f o r a p p l ica t ion s tha t p r og ra m t h e ad5243 /ad5258 a t t h e f a c t or y , a n a l o g d e v i c e s of f e r s d e v i c e pro g r a m m i n g s o f t w a re r u n n i ng on w i nd ow s ? n t / 2 0 0 0 / x p op e r a t i n g s y ste m s . t h i s s o f t wa r e ef fe c t iv e l y r e places an y ext e r n al i 2 c c o n t r o l l ers, w h ich in t u r n enhan c es us ers sys t em s time-t o-ma rk et. an ad5243/ ad5248 e v al u a t i o n ki t an d s o f t wa r e a r e a v a i lable . th e ki t in cl ude s a cab l e a nd inst r u c t io n ma n u a l . 1 the terms digital potentiometer , vr , a n d rdac are us ed i nte rchange a bl y.
ad5243/ad5248 rev. 0 | page 2 of 20 table of contents electrical characteristics2.5 k? version ................................... 3 electrical characteristics10 k?, 50 k?, 100 k? versions ....... 4 timing characteristicsall versions ........................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 te s t c i rc u it s ..................................................................................... 12 theory of operation ...................................................................... 13 prog ramming t he var iable resi stor and volt age .................... 13 programming the potentiometer divider ............................... 14 esd protection ........................................................................... 14 terminal voltage operating range .......................................... 14 power-up sequence ................................................................... 14 layout and power supply bypassing ....................................... 14 constant bias to retain resistance setting ............................. 15 evaluation board ........................................................................ 15 i 2 c interface .................................................................................... 16 i 2 c compatible 2-wire serial bus ........................................... 16 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history revision 0: initial version
ad5243/ad5248 rev. 0 | page 3 of 20 electrical characteristics2.5 k? version v dd = 5 v 10%, or 3 v 10%; v a = +v dd ; v b = 0 v; ? 40c < t a < +125c; unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?2 0.1 +2 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?6 0.75 +6 lsb nominal resistor tolerance 3 ? r ab t a = 25c ?20 +55 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl ?1.5 0.1 +1.5 lsb integral nonlinearity inl ?2 0.6 +2 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff ?10 ?2.5 0 lsb zero-scale error v wzse code = 0x00 0 2 10 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a, c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 9 bandwidth ?3 db bw_2.5 k code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k?, r s = 0 3.2 nv/ hz see notes at end of section.
ad5243/ad5248 rev. 0 | page 4 of 20 electrical characteristics10 k?, 50 k?, 100 k? versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ? 40c < t a < 125c; unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?2.5 0.25 +2.5 lsb nominal resistor tolerance 3 ? r ab t a = 25c ?20 +20 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd =5 v 160 200 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl ?1 0.1 +1 lsb integral nonlinearity 4 inl ?1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff ?2.5 ?1 0 lsb zero-scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a, c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a power dissipation p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.0 8 %/% dynamic characteristics bandwidth ?3 db bw r ab = 10 k?/50 k?/100 k?, code = 0x80 600/100/4 0 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.1 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/ hz see notes at end of section.
ad5243/ad5248 rev. 0 | page 5 of 20 timing characteristicsall versions v dd = 5v 10%, or 3v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 3. parameter symbol conditions min typ 1 max unit i 2 c interface timing characteristics 10 (specifications apply to all parts) scl clock frequency f scl 0 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time 11 t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s see notes at end of section. notes 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (vw) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w ha ve no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v. 10 see timing diagrams for locati ons of measured values. 11 the maximum t hd:dat must be met only if the device does not stretch the low period (t low ) of the scl signal.
ad5243/ad5248 rev. 0 | page 6 of 2 0 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 4. parameter value v dd to gnd C0.3 v to +7 v v a , v b , v w to gn d v dd terminal curren t , ax to bx, ax to wx, bx to wx 1 pulsed 20 ma continuous 5 ma digital inputs and output volt age to gnd 0 v to 7 v operating tem p erature range C40c to +125c maximum junction temperature (t jmax ) 150c storage temperature C65c to +150c lead temperature (soldering, 10 sec) 300c t h ermal resista n ce 2 ja : msop-10 230c/w 1 maximum terminal curr ent is b o unde d by the maximum current handling of the s w itches , maxi m um power d i ss ip ation of the package, and maximum appl ied vol t age acros s any two of the a , b, and w terminal s at a given resi st a n ce. 2 p a ckage pow e r d i ss ipation = ( t jm ax ? t a )/ ja . s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5243/ad5248 rev. 0 | page 7 of 2 0 pin conf igura t ions and f u ncti on descriptions 10 9 8 7 1 2 3 4 b1 a1 w2 w1 b2 a2 sda gnd 6 5 scl v dd top view ad5243 04109-0-027 f i g u re 3. a d 52 43 p i n conf ig ur at io n 10 9 8 7 1 2 3 4 b1 ad0 w2 w1 b2 ad1 sda gnd 6 5 scl v dd top view ad5248 04109-0-028 f i g u re 4. a d 52 48 p i n conf ig ur at io n ta ble 5. a d 52 43 pi n f u nct i o n d e s c ri pt i o ns pin no. mnemonic description 1 b1 b1 terminal. 2 a1 a1 terminal. 3 w2 w2 terminal. 4 gnd digital ground. 5 v dd positive power s u pply. 6 scl serial clock input. positive edg e triggered. 7 sda serial data inpu t/ output. 8 a2 a2 terminal. 9 b2 b2 terminal. 10 w1 w1 terminal. ta ble 6. a d 52 48 pi n f u nct i o n d e s c ri pt i o ns pin no . m n e m o n i c d e s c r i p t i o n 1 b1 b1 terminal. 2 ad0 programmab l e ad d r ess bit 0 for m u ltiple package decodi ng. 3 w2 w2 terminal. 4 gnd digital ground. 5 v dd positive power s u pply. 6 scl serial clock input. positive edg e triggered. 7 sda serial data inpu t/ output. 8 ad1 programmab l e ad d r ess bit 1 for m u ltiple package decodi ng. 9 b2 b2 terminal. 10 w1 w1 terminal.
ad5243/ad5248 rev. 0 | page 8 of 2 0 typical perf orm ance cha r acte ristics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-030 v dd = 5.5v t a = 25c r ab = 10k ? v dd = 2.7v f i gur e 5 . r - inl vs . co de vs . sup p l y v o l t a g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-031 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 6 . r - dnl vs . c o de vs . sup p l y v o lta g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode inl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-032 r ab = 10k ? v dd = 2.7v t a = ? 40c, +25c, +85c, +125c v dd = 5.5v t a = ? 40c, +25c, +85 c, +125c f i gur e 7 . inl vs . code vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-033 v dd = 2.7v; t a = ? 40 c, +25c, +85c, +125c r ab = 10k ? f i gur e 8 . dnl vs . c o de vs . t e m p e r a t ur e ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 p o te ntiome te r mode inl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-034 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 9 . inl vs . code vs . sup p l y v o l t age s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-035 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 1 0 . dnl vs . c o de vs . sup p l y v o lta g e s
ad5243/ad5248 rev. 0 | page 9 of 2 0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-036 r ab = 10k ? v dd = 2.7v t a = ? 40 c, +25c, +85c, +125c v dd = 5.5v t a = ? 40c, +25c, +85 c, +125c f i gur e 1 1 . r - inl vs . c o de vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-037 v dd = 2.7v, 5.5v; t a = ? 40c, +25 c, +85c, +125c r ab = 10k ? f i gur e 1 2 . r - dnl vs . c o de vs . t e m p e r a t ur e ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 fse, fu ll- sc a l e er r o r ( l sb ) 1.0 1.5 2.0 temperature ( c) ?40 ? 25 ? 1 0 5 20 35 50 65 80 95 110 125 04109-0-038 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 13. f u ll- s c al e e rror v s . t e m p er a t ur e 0 0.75 1.50 2.25 3.00 3.75 4.50 zs e , ze ro-s cale e rror (ls b ) temperature ( c) ?40 ? 25 ? 1 0 5 20 35 50 65 80 95 110 125 04109-0-039 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 14. zero -s c a le e r r o r v s . t e mpe r a t ur e i dd , s u p p l y curre nt ( a) 0.1 1 10 ? 4 0 ? 7 2 6 5 9 9 2 125 temperature ( c) 04109-0-040 v dd = 5v v dd = 3v f i gure 15. sup p l y current v s . t e mper at ur e ?2 0 0 20 40 60 80 100 120 rheostat mode te mp co (ppm/ c) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-041 r ab = 10k ? v dd = 2.7v t a = ? 40c to +85 c, ? 40c to +125c v dd = 5.5v t a = ? 40c to +85c, ? 40c to +125 c f i g u re 16. r h e o s t at m o de t e mpco ?r wb /?t v s . code
ad5243/ad5248 rev. 0 | page 10 of 20 ?30 ?20 ?10 0 10 20 p o te ntiome te r mode te mp co (ppm/ c) 30 40 50 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04109-0-042 r ab = 10k ? v dd = 2.7v t a = ? 40c to +85c, ? 40c to +125c v dd = 5.5v t a = ? 40c to +85c, ? 40 c to +125 c f i gure 1 7 . p o tentiom e ter m o de t e m p co ?v wb /? t v s . code ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1m 100k 10m 04109-0-043 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 18. g a in vs. f r equ e nc y vs. c o d e , r ab = 2. 5 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04109-0-044 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 19. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04109-0-045 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 20. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04109-0-046 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 21. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1k 100k 1m 10m 04109-0-047 100k ? 60khz 50k ? 120khz 10k ? 570khz 2.5k ? 2.2mhz f i gure 22. C3 db bandwidth @ code = 0x80
ad5243/ad5248 rev. 0 | page 11 of 20 i dd , s u p p l y curre nt (ma) 0.01 1 0.1 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 digital input voltage (v) 04109-0-052 t a = 25c v dd = 2.7v v dd = 5.5v f i g u re 23. i dd vs . input v o l t a g e 04109-0-048 scl v w f i gure 2 4 . di g i ta l f eedthro u g h 04109-0-049 v w1 v w2 f i g u re 25. d i g i t a l c r os s t a l k 04109-0-051 v w1 v w2 f i g u re 26. a n a l og cr os s t alk 04109-0-053 v w f i g u re 27. m i ds c a l e gli t ch, cod e 0x 80 t o 0x 7f 04109-0-050 scl v w f i gure 2 8 . la r g e s i gna l s e ttli n g t i m e
ad5243/ad5248 rev. 0 | page 12 of 20 test circuits f i g u re 2 9 t h rou g h f i g u re 3 5 i l lu st r a te t h e te st c i rc u i ts t h a t de f i ne t h e te st c o ndi t i ons u s e d i n t h e p r o d u c t sp e c if ic a t ion t a bl es. 04109-0-003 v ms a w b dut v+ v+ = v dd 1lsb = v+/2 n f i gure 29. t e s t c i rc uit for p o tenti o meter d i v i de r n o nl in ea rit y e r r o r (inl, dnl) 04109-0-004 no connect i w v ms a w b dut f i gure 30. t e s t c i rc uit for r e s i s t or p o s i tion non l i n e a r i t y e rror (r heo s ta t o p er a t ion; r - inl, r - dnl) 04109-0-005 v ms2 v ms1 v w a w b dut i w = v dd /r nominal r w = [v ms1 ? v ms2 ]/i w f i gur e 3 1 . t e st c i r c ui t fo r wi p e r resi st a n c e 04109-0-006 ? v ms % dut ( ) a w b v+ ? v dd % ? v ms ? v dd ? v dd v a v ms v+ = v dd 10% psrr (db) = 20 log pss (%/%) = f i gure 32. t e s t c i rc uit for p o w e r sup p l y s e nsit ivit y(ps s, pssr) 04109-0-009 +15v ? 15v w a 2.5v b v out offset gnd dut ad8610 v in f i gure 33. t e s t c i rc uit for g a in v s . f r eq uenc y 04109-0-010 w b v ss to v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v f i gu r e 3 4 . t e st ci r c u i t fo r i n cr em en ta l on re si sta n c e w b v cm i cm a nc gnd nc v dd dut nc = no connect 04109-0-011 f i g u re 35. t e s t c i rc uit f o r co m m o n -m ode l e ak ag e cur r e n t
ad5243/ad5248 rev. 0 | page 13 of 20 theor y of opera tion the ad5243/ad5248 a r e 256-p o si tio n dig i t a l l y co n t r o l l ed va r i a b le r e sis t o r (vr) de vices. an in t e r n al p o w e r - o n p r es et places t h e wi p e r a t mids cale d u r i n g p o w e r - on, w h ich sim p l i f i es t h e f a u l t condi t i on r e co v e r y at p o w e r- u p . progr a mm ing the v a riable resi st or and vo l t a g e r h eos t at ope r ation the n o minal r e sis t a n ce o f t h e rd a c b e tw e e n t e r m inals a and b is a v a i la b l e in 2.5 k?, 10 k?, 50 k?, a nd 100 k?. th e n o minal re s i st anc e ( r ab ) o f th e vr has 2 56 co n t ac t p o in ts acces s e d b y t h e w i p e r t e r m i n al , pl us t h e b ter m inal co n t ac t. the 8- b i t da t a in t h e rd a c l a tc h is deco ded t o s e lec t on e o f the 256 p o s s i b le se t t in g s . a w b a w b a w b 04109-0-012 f i g u re 36. r h e o s t at m o de conf ig ur at i o n a ssu min g t h a t a 10 k? p a r t is us e d , t h e w i p e r s f i rst co nne c t ion s t a r ts a t t h e b t e r m inal fo r da t a 0x00. b e ca us e t h er e is a 50 ? wi p e r co n t ac t r e sist a n ce, such a co nne c t io n y i el ds a mi nim u m o f 100 ? (2 5 0 ?) r e sis t a n ce betw een t e r m inals w an d b . th e s e con d co n n e c t i o n is t h e f i rst t a p p o in t, w h ich c o r r esp o n d s t o 139 ? (r wb = r ab /256 + 2 r w = 39 ? + 2 5 0 ?) f o r da ta 0x01. th e t h ird co nne c t io n is t h e n e xt t a p p o in t, r e p r es en t i n g 178 ? (2 39 ? + 2 50 ?) f o r da ta 0x02, an d s o o n . e a c h ls b da ta v a l u e in cr e a s e m o v e s th e wi p e r u p t h e r e sist o r ladder un til th e l a s t ta p p o in t is r e ac h e d a t 1 0 ,100 ? (r ab + 2 r w ). d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b 04109-0-013 f i gur e 3 7 . ad52 43 e q ui v a le nt rd a c cir c ui t t h e g e n e ral eq ua ti o n d e t e rm in in g th e d i g i tall y p r ogra m m e d o u t p u t r e s i s t a n ce bet w een w a n d b i s w ab wb r r d d r + = 2 256 ) ( (1) w h er e: d is th e decimal eq ui valen t o f t h e b i na r y co de l o ade d i n t h e 8-b i t rd a c r e g i s t er . r ab is t h e e n d - to -end r e sist an c e . r w i s t h e w i p e r re s i s t a n c e c o n t r i bu t e d by t h e o n re s i s t a n c e of th e in t e rn al swi t c h . i n s u mma r y , if r ab = 10 k? a nd t h e a t e r m ina l is o p en c i rc u i te d, t h e f o l l ow i n g output r e s i st an c e r wb is s e t fo r t h e indic a te d r d a c la tch co des. ta ble 7. c o des a n d corres p o ndi ng r wb resistan ce d (dec) r wb (?) output state 255 9,961 full scale (r ab ? 1 lsb + r w ) 128 5,060 midscale 1 139 1 lsb 0 100 zero scale (wipe r contact resistance) n o t e t h a t , i n t h e zer o -s ca le con d i t io n, a f i ni te wi p e r r e sist a n c e o f 100 ? is p r esen t. c a r e sh o u l d b e ta k e n t o limi t t h e c u r r en t f l o w b e tw e e n w a nd b i n t h is s t a t e t o a maxi m u m p u ls e c u r r en t o f n o m o r e than 20 ma. o t h e r w is e , deg r ada t ion o r p o s s i b le dest r u c t io n o f t h e i n ter n a l s w i t ch co n t ac t can o c c u r . si mi l a r to t h e me ch ani c a l p o te n t i o me te r , t h e re s i st a n c e of t h e rd a c bet w een th e w i per w a n d t e rm i n al a also p r od uces a dig i t a l l y co n t r o l l ed co m p lem e n t a r y r e sis t a n ce , r wa . w h e n t h es e t e r m ina l s a r e us e d , t h e b t e r m in a l ca n b e op e n e d . s e t t in g t h e re s i st anc e v a lu e f o r r wa st ar ts a t a max i m u m v a lu e of re s i st anc e a nd de cr e a s e s a s t h e d a t a lo ade d in t h e la tch i n cr e a s e s in va l u e. the ge n e ra l e q u a t i o n fo r t h is o p era t io n is w ab wa r r d d r + ? = 2 256 256 ) ( (2) fo r r ab = 10 k? a nd t h e b t e r m inal o p en c i r c ui ted , the f o l l ow i n g output re s i st anc e r wa is s e t fo r t h e i n d i ca t e d rd a c la t c h co de s. ta ble 8. co des a nd corr es po n d i n g r wa resist an ce d (dec) r wa (?) output state 255 139 full scale 128 5,060 midscale 1 9,961 1 lsb 0 10,060 zero scale
ad5243/ad5248 rev. 0 | page 14 of 20 t y p i ca l d e vice -to - de vice ma tchi n g is p r o c ess lo t dep e n d e n t and ma y va r y b y u p t o 30%. b e c a us e t h e r e sis t an ce e l em e n t is p r o c es s e d in thin f i lm t e chn o log y , th e c h a n g e in r ab wi t h t e m p era t ur e has a v e r y lo w 35 p p m/ c t e m p er a t ur e co ef f i cien t. progr a mm ing the po tent iome t e r divi der voltage o u tp ut ope r ation th e di g i t a l p o te n t i o me te r e a s i ly ge ne r a te s a volt age d i v i de r a t w i p e r - to - b a nd w i p e r - to - a prop or t i ona l to t h e i n put volt age a t a t o b . u n li k e t h e p o la r i ty o f v dd t o gnd , whic h m u s t be p o s i t i ve, volt ag e a c ro ss a to b , w to a , a nd w to b c a n b e a t ei t h er p o la r i ty . a v i w b v o 04109-0-014 f i gure 38. p o tentiometer m o de c o nf ig ur ation i f ig n o r i n g t h e e f fe c t o f t h e w i p e r r e sist a n ce fo r a p p r o x im a t ion, co nne c t in g t h e a ter m ina l to 5 v a nd t h e b ter m ina l to g r o u nd p r o d uces a n ou t p u t v o l t a g e a t the wi p e r - t o -b star tin g a t 0 v u p t o 1 ls b les s than 5 v . e a c h l s b o f v o l t a g e is eq u a l t o th e v o l t - a g e a p plie d acr o ss ter m ina l ab divide d b y t h e 2 56 p o si t i o n s o f t h e p o te n t iom e ter di vi der . t h e gen e r a l e q u a t i o n def i nin g t h e output vo lt ag e at v w wi th r e sp e c t t o g r o u n d f o r a n y valid in p u t v o l t a g e a p plie d t o t e r m ina l s a and b is b a w v d v d d v 256 256 256 ) ( ? + = (3) a m o r e acc u ra te calc u l a t io n, w h ich i n cl udes t h e ef fe c t o f wi p e r re s i st anc e , v w , i s b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = (4) o p er a t ion o f t h e dig i t a l p o ten t i o m e ter in t h e divider m o d e r e s u l t s in a m o r e acc u ra t e op era t io n o v er t e m p er a t ur e . u n li k e t h e rh e o s t a t m o de , t h e o u t p u t vol t a g e is de p e n d en t mainl y o n th e ra ti o o f th e in t e rn al r e si s t o r s r wa a nd r wb and n o t t h e a b s o l u t e v a l u es. ther efo r e , t h e tem p er a t ur e dr if t r e d u ces t o 15 p p m /c. esd pro t ec tion a l l d i g i t a l i n put s are prote c te d w i t h a s e r i e s of i n put re s i stor s a nd p a r a l l el z e n e r es d st r u c t ur es, sh o w n in f i gur e 39 a n d f i gur e 40. this a p p l ies t o t h e dig i tal in p u t p i n s s d a, scl, ad0, a nd ad1 (ad5 248 o n l y ). logic 340 ? gnd 04109-0-015 f i g u re 39. e s d pr ot ec t i o n of d i g i t a l p i ns a, b, w gnd 04109-0-016 f i g u re 40. e s d pr ot ec t i o n of r e s i s t o r t e r m in als terminal vol t a g e o p e r a t ing r a nge the ad5243/ad5248 v dd and g n d p o we r su p p ly de f i ne s t h e b o u nda r y co n d i t io n s fo r p r o p er 3-t e r m ina l d i g i t a l p o t e n t iom e - t e r o p era t ion. s u p pl y sig n als p r es en t on t e r m i n als a, b , a nd w th a t e x ceed v dd o r gnd a r e cl am p e d b y t h e in ter n al fo r w a r d b i as e d dio d es (s ee f i gur e 41). gnd a w b v dd 04109-0-017 f i g u re 41. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and g nd power-up sequence b e ca us e t h e esd p r o t e c t i on dio d es limi t t h e vol t a g e com p li ance a t t e r m inals a, b , a nd w (s e e f i gur e 41), i t is im p o r t a n t t o po w e r v dd /gnd bef o r e a p p l yin g a n y v o l t a g e to t e r m i n als a, b , a nd w ; o t h e r w i s e, t h e dio d e is fo r w a r d b i as e d such t h a t v dd is p o w e r e d uni n te n t io na l l y an d m a y a f fe c t t h e r e st o f t h e us er s cir c ui t. t h e id e a l p o w e r - u p s e q u en c e is in t h e fol l o w in g o r der : gnd , v dd , d i g i t a l i n p u t s , a n d t h e n v a , v b , a n d v w . t h e r e l a t i v e ord e r of p o we r i ng v a , v b , v w , a nd t h e dig i t a l i n p u ts is n o t im p o r t an t as lon g as t h e y a r e p o w e r e d a f t e r v dd /g nd . l a y o ut an d power s u ppl y b y p a ssing i t is g o o d p r ac tice t o em p l o y co m p ac t, minim u m lead len g t h la yo u t desig n . th e le ads t o th e in p u ts sh o u ld be as dir e c t as pos s i b le wi th a m i n i m u m co n d uct o r le n g th . g r o u n d p a th s s h o u ld ha v e lo w r e sis t a n ce an d l o w ind u c t an ce . s i mil a rl y , i t is al s o g o o d p r ac tic e t o b y p a s s the p o w e r s u p p lies wi t h q u ali t y ca p a ci t o rs f o r o p tim u m sta b ili t y . s u p p l y leads t o th e de vice s h o u l d b e b y p a s s e d wi th dis k o r c h i p cera mic c a p a ci t o rs o f 0.01 f t o 0.1 f . l o w es r 1 f t o 10 f ta n t al um o r e l ec tr o- ly t i c c a p a c i tors shou l d a l s o b e a p pl ie d a t t h e sup p l i e s to mini mi ze an y t r a n sien t dist urb a n c e an d lo w f r e q uen c y r i p p le (s e e f i gur e 42). n o te t h a t t h e di g i t a l g r o u nd sho u ld a l s o b e j o i n e d re motely to t h e an a l o g g r ou nd a t one p o i n t to mi ni m i z e th e gr o u n d bo un ce .
ad5243/ad5248 rev. 0 | page 15 of 20 v dd gnd v dd c3 10 f c1 0.1 f ad5243 + 04109-0-018 f i g u r e 4 2 . p o w e r su pp l y by pa s s i n g c o nst a nt bias t o ret a in resist ance set t ing f o r us ers wh o desir e n o n v ol a t ili t y b u t ca nn ot j u s t if y th e addi - tio n al cos t f o r th e eemem, t h e ad5243/ad52 48 ma y b e co n s ider e d as lo w cost a l t e r n a t iv es b y ma in t a in in g a con s t a n t b i as t o r e ta in t h e wi p e r s e t t in g. the ad5243/ad5248 a r e desig n e d sp e c if i c a l ly wi t h lo w p o w e r in mi n d , w h ich a l lo ws lo w p o w e r co n s um pt io n e v en i n b a t t e r y -o p e ra t e d s y s t em s. th e g r a p h i n f i gur e 43 dem o n s t r a t e s t h e p o w e r co nsum p t ion f r o m a 3.4 v 450 mahr l i -i o n c e l l ph on e b a t t er y , which is co nn ec ted to th e ad5243 /ad5248. the m e as ur emen t o v er time sh o w s tha t t h e d e vice dr a w s a p p r o x im a t ely 1.3 a an d consum es neg l ig ib l e p o w e r . o v er a co urs e o f 30 da ys , t h e b a t t e r y is deplet e d b y les s t h a n 2%, t h e ma jo r i ty o f w h ich i s d u e t o t h e i n t r in sic le aka g e c u r r en t o f t h e b a t t e r y i t s e lf. days battery life depleted 0 90% 92% 94% 96% 51 0 1 5 98% 100% 102% 104% 106% 108% 110% 20 25 30 04109-0-019 t a = 25 c f i gure 4 3 . ba tter y o p er a t i n g li fe d e p l etio n t h i s d e m o n s tra t e s th a t co n s ta n t l y b i a s in g t h e p o t e n t i o m e t e r i s n o t an i m p r ac t i ca l a p p r o a ch. m o st p o r t a b le d e v i ces do n o t r e q u ir e t h e r e mo val o f b a t t er ies fo r t h e p u r p os e o f cha r g i n g . al th o u g h the r e sis t a n ce s e t t in g o f th e ad5243/ad5248 is los t wh e n t h e b a t t e r y n eed s r e p l a c em en t , s u c h ev en t s occur ra th e r inf r e q uen t ly such t h a t t h is i n con v en ie n c e is j u st if ie d b y t h e lo w e r cos t a n d s m al ler size o f f e r e d b y the ad52 43/ad5248. i f a nd w h e n t o t a l p o w e r is los t , th e us er s h o u ld be p r o v ide d wi th a m e an s t o a d j u st t h e s e t t i n g accor d in g l y . e v al u a tion bo ard a n e v a l u a t i on b o ard, a l ong w i t h a l l ne c e ss ar y s o f t w a re, i s a v ai l - a b le t o p r og ra m th e ad5243/ad5248 f r o m a n y pc r u nnin g w i n d o w s 98/20 00/xp . th e g r a p hical us er in t e r f ace , as sh o w n in f i gur e 44, is st r a ig h t fo r w a r d and e a sy to us e. m o r e det a i l e d info r m a t io n is a v a i lab l e in t h e u s er ma n u a l , w h i c h com e s wi t h th e boa r d . f i g u re 44. a d 5 2 4 3 ev aluat i on bo ar d s o f t w a r e the ad5243/ad5248 s t a r t a t mids cale u p o n p o w e r - u p . t o in cr e m e n t o r de cr em e n t t h e r e sis t an ce , t h e us er ma y sim p l y m o v e t h e s c r o l l b a rs o n t h e lef t . t o wr i t e an y sp e c if ic val u e , t h e us er s h o u ld us e t h e b i t p a t t er n i n t h e u p p e r s c r e en an d p r es s t h e r u n b u t t on. t h e fo r m a t o f wr i t in g da t a to t h e de vice is sh own i n t a b l e 9. t o r e a d t h e d a ta o u t f r o m th e de v i ce , th e use r ca n sim p l y p r es s the re ad b u t t on. th e fo r m a t o f t h e r e ad b i ts is s h own in t a b l e 10.
ad5243/ad5248 rev. 0 | page 16 of 20 i 2 c interface i 2 c compatible 2-wire serial bus the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 46). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this bit deter- mines whether data is read from or written to the slave device). the ad5243 has a fixed slave address byte, while the ad5248 has two configurable address bits ad0 and ad1 (see table 9). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. on the other hand, if the r/ w bit is low, the master writes to the slave device. 2. in the write mode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is the rdac subaddress select bit. a logic low selects channel 1 and a logic high selects channel 2. the second msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previ- ous setting is applied to the rdac. also, during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the remainder of the bits in the instruction byte are dont care bits (see table 9). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 46 and figure 47). 3. in the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, eight data bits are followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 48 and figure 49). note that the channel of interest is the one that is previ- ously selected in the write mode. in the case where users need to read the rdac values of both channels, they need to program the first channel in the write mode and then change to the read mode to read the first channel value. after that, they need to change back to the write mode with the second channel selected and read the second channel value in the read mode again. it is not necessary for users to issue the frame 3 data byte in the write mode for subse- quent readback operation. users should refer to figure 48 and figure 49 for the programming format. 4. after all data bits have been read or written, a stop condi- tion is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the tenth clock pulse to establish a stop condition (see figure 46 and figure 47). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the tenth clock pulse, which goes high to establish a stop condition (see figure 48 and figure 49). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in the write mode, the rdac output updates on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5243/ad5248 rev. 0 | page 17 of 20 table 9. write mode ad52 43 s 0 1 0 1 1 1 1 w a a 0 sd x x x x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave ad dress byt e instruction byte data byte ad52 48 s 0 1 0 1 1 a d 1 a d 0 w a a 0 sd x x x x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave ad dress byt e instruction byte data byte table 10. read mode ad52 43 s 0 1 0 1 1 1 1 r a d7 d6 d5 d4 d3 d2 d1 d0 a p sl ave a d dr ess byte data byte ad52 48 s 0 1 0 1 1 a d 1 a d 0 r a d7 d6 d5 d4 d3 d2 d1 d0 a p sl ave a d dr ess byte data byte l e g e n d s = start cond ition. p = st op con d i t i o n . a = ackn owl e dg e. x = do nt care. w = write. ad 0, ad 1 = pa cka g e pi n programmabl e address bits . r = rea d . a 0 = rda c subad d re ss s e le ct bit. sd = sh ut down c o n n e ct s wi per t o b t e rm i n a l a n d o p e n circuits a te rminal . it d o e s no t change co nte nts of wipe r r e gister. d7, d6, d5, d4, d3, d2, d1, d0 = data bits . 04109-0-021 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p f i g u re 45. i 2 c inter f a c e d e ta il ed ti mi ng di a g r a m 04109-0-022 scl start by master sda 01 1 frame 1 slave address byte 0 1111 frame 2 instruction byte ack by ad5243 r/w a0 sd x x x x 1 9 d7 d6 d5 d4 d3 ack by ad5243 frame 3 data byte 1 9 x stop by master 9 d2 d1 d0 ack by ad5243 x f i g u re 46. w r it ing t o t h e r d a c r e g i s t e r ?a d5 24 3
ad5243/ad5248 rev. 0 | page 18 of 20 04109-0-023 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5248 r/w a0 sd x x x x 1 9 d7 d6 d5 d4 d3 ack by ad5248 frame 3 data byte 1 9 x stop by master 9 d2 d1 d0 ack by ad5248 x f i g u re 47. w r it ing t o t h e r d a c r e g i s t e r a d5 24 8 04109-0-024 scl start by master stop by master sda 01 1 frame 1 slave address byte 01 1 1 1 frame 2 rdac register ack by ad5243 r/w d7 d6 d4 d3 d2 d1 d0 1 9 no ack by master 9 d5 f i g u re 48. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de a d5 24 3 04109-0-025 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 rdac register ack by ad5248 r/w d7 d6 d4 d3 d2 d1 d0 1 99 d5 stop by master no ack by master f i g u re 49. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de a d5 24 8 multiple dev i ces on one bu s (applies onl y to ad5248) f i gur e 50 s h o w s f o ur ad5248 devices o n t h e s a m e s e r i al b u s. e a ch has a dif f er en t s l a v e addr e s s, b e ca us e t h e st a t es o f t h eir ad0 and ad1 p i n s a r e dif f er en t. this al lo ws eac h device on th e b u s to b e w r it te n to or re a d f r om i n de p e nde n t l y . the m a st e r d e v i c e output bu s l i ne d r ive r s a r e op e n - d r a i n pu l l - d ow ns i n a full y i 2 c co m p a t i b le in t e r f ac e . sda sda ad1 ad0 master scl scl ad5248 sda ad1 ad0 scl ad5248 sda ad1 ad0 scl ad5248 sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5248 04109-0-026 f i g u re 50. m u lt ip le a d 52 48 d e v i ces on o n e i 2 c b u s
ad5243/ad5248 rev. 0 | page 19 of 20 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba f i gure 51. 1 0 -l ead m i ni s m al l o u tl ine p a ck ag e [msop ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model r ab temperature package descri ption package option branding ad5243brm2.5 2.5 k? ?40c to +125c msop-10 rm-10 d0l ad5243brm2.5- rl7 2.5 k? ?40c to +125c msop-10 rm-10 d0l ad5243brm10 10 k? ?40c to +125c msop-10 rm-10 d0m ad5243brm10- rl7 10 k? ?40c to +125c msop-10 rm-10 d0m ad5243brm50 50 k? ?40c to +125c msop-10 rm-10 d0n ad5243brm50- rl7 50 k? ?40c to +125c msop-10 rm-10 d0n ad5243brm100 100 k? ?40c to +125c msop-10 rm-10 d0p ad5243brm100 -rl7 100 k? ?40c to +125c msop-10 rm-10 d0p ad5243eval see note 1 evaluation boar d ad5248brm2.5 2.5 k? ?40c to +125c msop-10 rm-10 d1f ad5248brm2.5- rl7 2.5 k? ?40c to +125c msop-10 rm-10 d1f ad5248brm10 10 k? ?40c to +125c msop-10 rm-10 d1g ad5248brm10- rl7 10 k? ?40c to +125c msop-10 rm-10 d1g ad5248brm50 50 k? ?40c to +125c msop-10 rm-10 d1h ad5248brm50- rl7 50 k? ?40c to +125c msop-10 rm-10 d1h ad5248brm100 100 k? ?40c to +125c msop-10 rm-10 d1j ad5248brm100 -rl7 100 k? ?40c to +125c msop-10 rm-10 d1j ad5248eval see note 1 evaluation boar d 1 th e evaluat i on board is s h ippe d with the 10 k ? r ab re si st or opt i on ; h o w e ver, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le r e si st or va lu e opt i on s.
ad5243/ad5248 rev. 0 | page 20 of 20 notes purch a s e o f li cen s ed i 2 c com p on en t s of an a l og d e vi ces or on e o f i t s sub l i c e n sed a ssoci a t ed c o m p a n i e s con v eys a li cen s e f o r t h e purc h a ser un d e r t h e ph i li ps i 2 c p a te nt rights to use the s e co mpo n e n t s in an i 2 c sy st em , p r ovi d e d t h a t t h e sy st em con f orm s t o t h e i 2 c st a n da rd sp e c i f i c a t i o n a s de fi n e d by ph i l i p s. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04109C0C 1/04(0)

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